CONFERENCE-AT-A-GLANCE
Sunday, September 25 - Tutorial Workshops
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Morning Workshops
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Tutorial Track A
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Tutorial Track B
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8:00 a.m. - 12:00 a.m.
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SA1 Models and Tools for Dynamic Reconfiguration of FPGAs A. Donlin, Xilinx Research Labs, J.
Becker, M. Hübner, University of Karlsruhe
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SB1 Standards-Compliant IP-Based ASIC and SOC Design A. Hekmatpour, K. Goodnow, H. Shah, IBM Corporation
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Afternoon Workshops
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1:00 pm - 3:00 pm
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SA2 Serial Rapid-IO: Benefiting System Interconnects T. Scheckel, Texas Instruments Inc.
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SB2 High-performance on-chip interconnect circuit technologies for sub-65nm CMOS H. Kaul, Intel Corporation
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3:30 p.m. - 5:30 p.m.
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SA3 DSPs for Communications, Video Infrastructure and Audio N. Seshan, G. Martinez,
T. Hiers, A. Seely, Z. Nikolic, Texas Instruments Inc.
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SB3 Challenges in Nanometer SOC SRAM Designs S. Chung, TSMC
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Monday, September 26
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Registration 7:00 a.m. - 5:00 p.m.
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Plenary Session 8:30 a.m. - 11:30 a.m.
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Opening Remarks: Dong Ha, General Conference Chair Technical Program Overview: Ram Krishnamurthy, Technical Program Chair Keynote Presentation: Dr. Johannes M.C. (Hans) Stork, Senior Vice President and Chief Technology Officer, Texas Instruments,
Inc. Plenary Presentations: Dr. Ivo Bolsens, Vice President and Chief Technology Officer, Xilinx Inc.,
Dr. Jacques Benkoski, Entrepreneur in Residence, US Venture Partners
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Lunch 11:30 a.m. - 1:00 p.m.
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(on your own)
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Technical Sessions 1:00 p.m. - 2:40 p.m.
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Track A MA2: Frequency Synthesizers and Generators
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Track B MB2: Physical and Microarchitecture Design Methods
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3:00 p.m. - 4:45 p.m.
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MA3: Analog Design for SOC
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MB3: DFT and Test Techniques
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4:45 p.m. - 6:00 p.m.
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POSTER SESSION
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6:00 p.m. - 8:00 p.m.
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Conference Reception
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Tuesday, September 27
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Registration 7:30 a.m. - 5:00 p.m.
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Technical Sessions 8:30 a.m. - 10:10 a.m.
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Track A TA1: SOC Architectures and Design Methods
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Track B TB1: Low Power Design
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10:30 a.m. - 11:45 a.m.
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TA2: Embedded Systems, Sensors and MEMS
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Luncheon 11:45 a.m. - 1:15 p.m.
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Guest speaker: Rajesh Galivanche, Intel Corporation
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Technical Sessions 1:40 p.m. - 3:20 p.m
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Track A TA3: Radio Frequency and Optical Circuits
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Track B TB3: Signal Integrity and On-Chip Interconnections
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3:30 p.m. - 5:30 p.m.
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Panel Discussion
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Wednesday, September 15
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Registration 8:00 a.m. - 3:30 p.m.
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Technical Sessions 8:30 a.m. - 10:10 a.m.
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Track A WA1: High-End SoC Challenges I: From IP Reuse to Sign-Off
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Track B WB1: SOC Configurable Architectures and Runtime Support
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10:30 a.m. - 11:45 a.m.
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WA2: High-End SoC Challenges II: Design Issues
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WB2: FPGAs for Security and SIMD Applications
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Lunch 11:45 a.m. - 1:30 p.m.
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(on your own)
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Technical Sessions 1:30 p.m. - 3:10 p.m.
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Track A WA3: Wireless/Wireline Communication and Signal Processing
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Track B WB3: High Performance Circuits and Systems
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