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CONFERENCE-AT-A-GLANCE

Sunday, September 25 - Tutorial Workshops

Morning Workshops

Tutorial Track A

Tutorial Track B

8:00 a.m. -
12:00 a.m.

SA1
Models and Tools for Dynamic Reconfiguration of FPGAs
A. Donlin, Xilinx Research Labs, J. Becker, M. Hübner, University of Karlsruhe

SB1
Standards-Compliant IP-Based ASIC and SOC Design
A. Hekmatpour, K. Goodnow, H. Shah, IBM Corporation

Afternoon Workshops

 

 

1:00 pm -
3:00 pm

SA2
Serial Rapid-IO: Benefiting System Interconnects
T. Scheckel, Texas Instruments Inc.

SB2
High-performance on-chip interconnect circuit technologies for sub-65nm CMOS
H. Kaul, Intel Corporation

3:30 p.m. -
5:30 p.m.

SA3
DSPs for Communications, Video Infrastructure and Audio
N. Seshan, G. Martinez, T. Hiers, A. Seely, Z. Nikolic, Texas Instruments Inc.

SB3
Challenges in Nanometer SOC SRAM Designs
S. Chung, TSMC

Monday, September 26

Registration
7:00 a.m. -
5:00 p.m.

 

 

 

Plenary Session
8:30 a.m. -
11:30 a.m.

Opening Remarks:
   Dong Ha, General Conference Chair
Technical Program Overview:
   Ram Krishnamurthy, Technical Program Chair
Keynote Presentation:
   Dr. Johannes M.C. (Hans) Stork, Senior Vice President and Chief Technology Officer, Texas Instruments, Inc.
Plenary Presentations:
   Dr. Ivo Bolsens, Vice President and Chief Technology Officer, Xilinx Inc.,
Dr. Jacques Benkoski, Entrepreneur in Residence, US Venture Partners

Lunch
11:30 a.m. -
1:00 p.m.

(on your own)

Technical Sessions
1:00 p.m. -
2:40 p.m.

Track A
MA2:
Frequency Synthesizers and Generators

Track B
MB2:
Physical and Microarchitecture Design Methods

3:00 p.m. -
4:45 p.m.

MA3:
Analog Design for SOC

MB3:
DFT and Test Techniques

4:45 p.m. -
6:00 p.m.

POSTER SESSION

6:00 p.m. -
8:00 p.m.

Conference Reception

Tuesday, September 27

Registration
7:30 a.m. -
5:00 p.m.

 

 

Technical Sessions
8:30 a.m. -
10:10 a.m.

Track A
TA1: SOC Architectures and Design Methods

Track B
TB1: Low Power Design

10:30 a.m. -
11:45 a.m.

TA2: Embedded Systems, Sensors and MEMS

TB2: Low Power Memory

Luncheon
11:45 a.m. -
1:15 p.m.

Guest speaker:
Rajesh Galivanche, Intel Corporation

Technical Sessions
1:40 p.m. -
3:20 p.m

Track A
TA3: Radio Frequency and Optical Circuits

Track B
TB3: Signal Integrity and On-Chip Interconnections

3:30 p.m. -
5:30 p.m.

Panel Discussion

Wednesday, September 15

Registration
8:00 a.m. -
3:30 p.m.

 

 

Technical Sessions
8:30 a.m. -
10:10 a.m.

Track A
WA1: High-End SoC Challenges I: From IP Reuse to Sign-Off

Track B
WB1: SOC Configurable Architectures and Runtime Support

10:30 a.m. -
11:45 a.m.

WA2: High-End SoC Challenges II: Design Issues

WB2: FPGAs for Security and SIMD Applications

Lunch
11:45 a.m. - 1:30 p.m.

(on your own)

Technical Sessions
1:30 p.m. -
3:10 p.m.

Track A
WA3: Wireless/Wireline Communication and Signal Processing

Track B
WB3: High Performance Circuits and Systems