Will the technical realities and economics presented by 65nm and 45nm silicon technologies drive system applications toward fully integrated SoC implementations or alternative, dis-integrated solutions? For an answer to this question, visit the panel discussion on Tuesday afternoon.
Corporate sponsors of our conference may be present with tabletop displays. For more information on corporate sponsorship, please contact the Conference Office.
Like in our previous conferences, there will be several half-day tutorials on Sunday.
Dr. Johannes M.C. (Hans) Stork
Senior Vice President and Chief Technical Officer,
Texas Instruments, Inc.
“Advanced CMOS Technology for Digital Communication Systems”
Dr. Stork is Senior Vice President, and Chief Technology officer, of Texas Instruments. As Director of the Silicon Technology Development organization, his primary responsibilities are the development of advanced CMOS, packaging and mixed signal process technologies. He joined Texas Instruments in September 2001, as Vice President and Director of Silicon Technology Research.
Prior to joining Texas Instruments, Dr. Stork was Director of the Internet Systems and Storage Lab at HP Laboratories, Hewlett-Packard in Palo Alto, California from 1999 until 2001. The IS&S Lab focused on highly scalable, dynamic, federated computer and storage systems. After joining Hewlett-Packard in 1994, Dr. Stork held the position of Director of the ULSI Research Lab between 1995 and 1999. This laboratory was established in 1994 and closed in 1999 with the split between Agilent and Hewlett-Packard. The operational staff of the 40,000 square foot, Class 1, clean room facility improved the productivity per person hour to the best recorded in HP's facilities. During his leadership the researchers of the ULSI Lab developed a high performance 0.18 um CMOS technology with Al/low-k interconnect, and developed and transferred then world's lowest dark-current CMOS image sensors and technology to Agilent's image component division. The ULSI Research Lab demonstrated the world's smallest FRAM cell feasibility jointly with TI and Applied Materials in 1999.
Dr. Stork started his professional career in 1982 at IBM's T.J.Watson Research Center, researching advanced bipolar technology and circuits. In 1987, he established and managed an Exploratory Devices group. This group explored and demonstrated SiGe HBTs, resulting in new speed records at device and circuit level, and presented invited talks at all major conferences including six papers at a single IEDM conference. Within 10 years, this SiGe technology was transferred to manufacturing and established IBM's entry in high-speed communication technologies. In 1990, Hans became manager of the Bipolar Devices group, and led one of the task forces on high-end computing that resulted in IBM's change in mainframe strategy. From 1992 to 1994, he assumed responsibility for the Exploratory Device and Technology programs at IBM Research. His teams demonstrated CMOS process technologies at 0.1 um channel lengths with world record speed performance, supported by an extensive E-beam lithography facility. They also published the first extensive simulations of double-gate devices as the best structure to the ultimate scaling challenges of FETs.
Hans was awarded two Outstanding Technical Achievement Awards from IBM. He has written or co-authored over 90 cited papers and holds eleven US patents. He was elected IEEE Fellow in 1994 for his contributions to SiGe devices and technology. As a fellow member of the IEEE Electron Devices Society, Hans has served as a member of the 1988 BCTM program committee, was on the VLSI Technology Symposium program committee from 1986 to 1992, and was publications/publicity chairman for the 1990-1992 Technology and Circuit Symposia, publicity (vice) chairman for the (1991) 1992 IEDM, and technical program committee member of the 1994 IEDM. Hans was EDS editor of the Circuits and Devices magazine from 1993 to 1995, and was on the technical program committee of the Symposium on Low Power Electronics in 1995 and 1996.
Dr. Stork serves on the Board of Directors for International Sematech (ISMT) since 2002, and for the Semiconductor Research Corporation (SRC) since 1999. Prior to that he was a member of the Executive Advisory Boards for both Sematech and the SRC from 1997-1999. He has been a member of the SIA Technology Strategy Committee since 1999. In 2000-2001, he participated as a technical advisor to Government efforts on high performance computing benchmarks and the national security issues emerging from Internet computing.
Dr. Stork was born in Soest, The Netherlands, and received the Ingenieur degree in electrical engineering from Delft University of Technology, Delft, The Netherlands, and holds a PhD from Stanford University. His PhD and Ir. theses concerned the fabrication, modeling and measurement of Static Induction Transistors, non-volatile NMOS devices and junction FET CCDs.
Dr. Ivo Bolsens joined Xilinx in June 2001 as vice president and chief technology officer (CTO). He is responsible for identifying Xilinx technologies and talent as well as heading up the Xilinx Research Laboratories, which focus on advanced research in the area of programmable logic.
Dr. Bolsens came to Xilinx from the Belgium-based research center IMEC, where he was vice president of information and communication systems. He began there in 1984, holding various positions of increasing responsibility. His research included the development of knowledge-based verification for VLSI circuits, design of digital signal processing applications, and wireless communication terminals. He also headed the research on design technology for high level synthesis of DSP hardware, HW/SW co-design and system-on-chip design.
Bolsens earned his master's degree in electrical engineering and his Ph.D. in applied science from the Catholic University of Leuven in Belgium. He is author and co-author of more than 100 papers in the field of VLSI design, CAD, embedded system design, and wireless communication. He is also co-author of the book, "High Level Synthesis for Real Time Digital Signal Processing."
Dr. Benkoski joined US Venture Partners in 2005 as Entrepreneur in Residence following the acquisition of Monterey Designs Systems by Synopsys. He led Monterey as CEO & President since 1999 and during that tenure the company´ramped up to 150 employees and had its products adopted by most semiconductor companies in North America, Europe and Japan. Previously he was Vice President of European Operations for EPIC Design Technology and has also held various research, marketing, sales and general management positions at Synopsys, STMicroelectronics, IMEC, and IBM. Dr. Benkoski has been a Director of the EDA Consortium since 2001 and is Chairman of the Board of Certess. He has received his B.Sc. in computer engineering from the Technion, Israel Institute of Technology and his M.Sc. and Ph.D. degrees in electrical and computer engineering from Carnegie Mellon University and has written over 30 technical papers.
“Test Challenges for Nanometer Designs”
Rajesh Galivanche is a Principal Engineer and Manager of Advanced Test Technology development team in the Technology and Manufacturing Group at Intel. His group researches into Advanced Test and CAD methods for testing, debug and diagnosis of semiconductor devices. Rajesh has been with Intel for the last 10 years and before that he worked at Motorola, LSI Logic Corporation, and Sunrise Test Systems (which was later acquired by Viewlogic/Synopsys).
“Will the technical realities and economics presented by 65nm and 45nm silicon technologies drive system applications toward fully integrated SoC implementations or alternative, dis-integrated solutions?”
Moderator: Tom Bednar
ASIC Product Development,
Tim Henricks, Vice President, Engineering Services, Cadence
Joachim Kunkel, Vice President, Engineering, Synopsys
Frederic Reblewski, Chairman and CEO, M2000
Peter Rickert, Fellow, Director, ASP program Mgmt, Texas Instruments
Mark Templeton, Chief Strategy Officer, ARM
Arnie Tran, Architecture Lead, SOC Design Center, IBM
Abstract: The scale of advanced silicon technologies brings the possibility of very high levels of integration into consideration. 100M circuits, or more, could theoretically be integrated on a manufacturable die size. Improvements in overall performance, power consumption, and space efficiency could follow from such a silicon integration. However, the raw potential capability does not necessarily make these kinds of solutions technically practical or economically viable. Will technical issues such as, process complexity and variation, yield, and data volume prevent such large scale integration from being practical? Will economic factors such as mask costs, IP costs, time to market pressures, and functional flexibility requirements drive a solution? What emerging technologies,tools, or architectures will influence future integration strategies?